1. Field
Example embodiments relate to memory devices. Other example embodiments relate to memory devices capable of reducing lateral movement of charges.
2. Description of the Related Art
Among semiconductor memory devices, nonvolatile memory devices retain stored data even if a power supply is interrupted. A floating-gate flash memory, which operates using charges stored in a floating gate formed of polysilicon (poly-Si), is commercially available as a high-capacity nonvolatile memory.
Memory cells of the flash memory may be divided into a single-level cell (SLC) in which two write states (1 and 0) are written and a multi-level cell (MLC) in which at least four write states (e.g., 11, 01, 00, and 10) are written. MLC technology may be necessary for high-capacity NAND-type flash memories and NOR-type flash memories.
In an MLC operation mode, the distribution of threshold voltages Vth of memory cells corresponding to respective write states should be low in order to separately recognize the respective write states.
In a floating-gate flash memory, as a cell size decreases, controlling the distribution of threshold voltages becomes more difficult due to an increase in coupling between cells (particularly, coupling between floating gates).
In recent years, in order to reduce coupling between cells, a charge trap flash (CTF) memory has been researched wherein an insulating layer, that has a charge trap site (e.g., a silicon nitride (Si3N4) charge trap site) capable of trapping charges instead of a floating gate, is used as a charge storage layer (i.e., a charge trap layer).
In the CTF memory, if an electrostatic force between charges stored in adjacent cells is increased, the trapped charges may tunnel, or hop, between trap sites present in the insulating layer because charges are trapped in the insulating layer (e.g., the Si3N4 having a charge trap site).
In order to program the CTF memory, a voltage of 0V is applied to an active region corresponding to a selected bit line, a power supply voltage Vcc is applied to an unselected bit line, a program voltage Vpgm is applied to a selected word line and a pass voltage Vpass is applied to an unselected word line. Due to the program operation, electrons are injected through a tunneling oxide layer only to cells where the selected bit line overlaps the selected word line. The injected electrons are trapped and stored in trap sites scattered in the charge trap layer.
During a program operation of an MLC, the program operation may be repeated by boosting program voltage Vpgm to a specific level by stages in order to reduce the distribution of threshold voltages Vth of program cells corresponding to respective levels. This is called an incremental step pulse program (ISPP) method.
If stored data is erased from the CTF memory, an erase voltage VERS is applied to a bulk portion and a voltage of 0V is applied to control gates of all word lines so that all memory cells (i.e., a memory block) connected by the bulk portion may be erased at one time. In this case, a block of a memory device is formed of a plurality of pages. For example, if a plurality of memory cells connected in series to a single bit line constitute a single string in a NAND-type flash memory, the pages may be classified on the basis of memory cells connected to a single word line. A read operation and a program operation may be performed in page units, and an erase operation may be performed in block units.
During the erase operation, holes may be injected from the active region through the tunneling oxide layer to the charge trap layer and neutralize the electrons stored in the memory cell during the program operation.
Because all cells included in a single block are erased at the same time, the distribution of threshold voltages Vth of the erased cells may not be controlled, and thus have a high value unlike in the program operation. Considering this characteristic, the erase operation may be performed so as to sufficiently erase all the memory cells. As such, the distribution of the threshold voltages Vth of the erased cells may have a negative value within a range of 0 to −3V.
Because a programmed memory cell has a positive threshold voltage Vth, there is a big charge potential difference between the programmed cell and the erased cell. Due to the potential difference, the charges stored in the charge trap layer may move toward the word line.
If the stored charges gradually move toward the word line after the program operation, the threshold voltage Vth of the programmed memory cell gradually decreases so that stored data may be lost. The movement of the charges stored in the charge trap layer towards the word line may degrade the reliability of the CTF memory.